1. Field of the Invention
This invention relates to a display and its driving circuit, and more particularly, the invention relates to a source driver, a source driver array, and driving circuit and display with the array.
2. Description of Related Art
Liquid crystal Display (LCD) has the characteristics being light, thin, small volume, low radiation, and saving power. These characteristics allow the space used in office area or home area to be saved, and also reduce the eye fatigue due to a long time of viewing on it. Therefore, in the planar display apparatus, LCD has the potential to replace the conventional CRT. However, as image resolution is more and more requested, it means that the data size for each frame of image is accordingly getting large. Therefore, the operation frequency of drivers for the planar display apparatus also increases.
Referring to FIG. 1, it is a block diagram, schematically illustrating a conventional AMTFT (Active Matrix Thin Film Transistor (TFT)) LCD 100. This LCD 100 includes a TFT LCD panel 101, a source driver array 102 composed of several source drivers, a gate driver array 103 composed of several gate drivers, a power supplier 104, and a timing controller 105. The timing controller 105 supplies the operation clock CLK (see FIG. 1) to the source drivers of the source driver array 102 and the gate drivers of the gate driver array 103. At the same time, the timing controller 105 issues a vertical synchronous signal to the gate driver array 103, and issues a horizontal synchronous signal to the source driver array 102 and the gate driver array 103. For the descriptions, the control signals for the source driver array 102 and the gate driver array 103 are respectively called the source control signal and the gate control signal, as shown in FIG. 1. The displaying data to be displayed on the TFT LCD panel 101 are first entering the timing controller 105, and then are sent to the source driver array 102 via the timing controller 105. The source drivers in the source driver array 102 obtain the display data, and the displaying data is converted by a digital-to-analog converter in accordance with the horizontal synchronous signal supplied by the timing controller 105. After then, the source drivers export a gray-level voltage to the TFT LCD panel 101 for displaying image.
Referring to FIG. 2, it is a drawing, schematically illustrating a coupling relation between a timing controller 210 and a source driver array 220 in a conventional active-matrix TFT LCD. This source driver array 220 includes n number of source drivers (2201˜220n). The timing controller 210 connects with each of the source drivers 2201˜220n, and respectively supplies a start pulse signal DIO1, a operation clock CLK, a display data signal DATA and a horizontal latch signal LD to each of the source drivers 2201˜220n, as shown in FIG. 2. The operation clock CLK, the display data signal DATA and the horizontal latch signal LD are transmitted in the same bus, and each of the source driver 2201˜220n is connected to the bus for receiving signals. The pulse signal DIO1 is then connected by the connection manner of point to point, and is latched according to the operation clock CLK, so as to serve as the control signal for the data signal DATA in sequential distribution. When the line buffer is full in data latch, it then issues a start pulse signal DIO2, for supplying to the next source driver in use. The expansion of display image is achieved by using this manner of data in a series sequence.
FIG. 3 is a block diagram, schematically illustrating a conventional source driver of the Active Matrix Thin Film Transistor LCD. This source driver 300 includes a shift register 310, a sampling register 320 coupled to a data latch unit 330, a hold register 340, a level shift 350, a digital-to-analog converter (DAC) unit 360 and a output buffer 370. The DAC unit 360 is coupled to a gamma voltage generator 380.
The shift register 310 receives a start pulse signal DIO1 being externally input. The start pulse signal DIO1 is latched, so as to serve as the control signal for data sequential distribution. The display data signal DATA is then transmitted to the sampling register 320 via the data latch unit 330 and the data bus. This hold register 340 also receives the horizontal latch signal (LD). After the level shift unit 350 adjusts voltages of the display data signals, the signals are transmitted to the DAC unit 360. The Gamma voltage generator 380 receives a gamma voltage from external, and accordingly exports an output to the DAC unit 360 to serve as a reference for adjusting the analog signal. The adjusted display data signal is transmitted to the TFT LCD panel via the output buffer 370.
However, the bottleneck of this method is the path difference between the start pulse signal DIO1 at the receiving terminal and the operation clock signal CLK. It often causes latch error of the start pulse signal, and then limits the maximum operation frequency. The current method can only reach to about 100 MHz.
Referring to FIG. 4, it is a timing chart, schematically illustrating the timing sequence of the conventional source driver of an active TFT LCD. As shown in FIG. 4, at the time T1, the source driver receives the horizontal latch signal (LD). At the time T2, the source driver receives the start pulse signal DIO1, and performs the latch according to the operation clock CLK, so as to serve the control signal of the data sequential distribution. When the line buffer is data latch full, it sends a start pulse signal DIO2 as the output for use by the next source driver, such as at the time T3. The scheme of one after one in sequence continues until the display data of one horizontal line are completely latched. At this moment, the timing controller issues the horizontal latch signal LD to convert the data in line buffer from digital to analog, and then a gray level voltage is exported to the TFT LCD panel.